The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. One of the primary enabling factors of this growth has been the ability of optical lithography to steadily decrease the smallest feature size that can be formed as part of the integrated circuit pattern. The steady decline in feature size and cost and the corresponding increase in the density of features printed per circuit are commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask or reticle (mask and reticle are used interchangeably herein), then projecting an image from the mask onto a resist-covered semiconductor wafer in order to create a pattern that matches the design intent of defining functional elements, such as transistor gates, contacts etc., on the wafer. The more times a master pattern is successfully replicated on a wafer within the design specifications, the lower the cost per finished device or “chip” will be. Until recently, the mask pattern has been an almost exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern, due to an imaging reduction ratio of the exposure tool. The mask is typically formed by depositing and patterning a light absorbing material on quartz or another transparent substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the wafers. The light is transmitted through clear areas of the mask, but is attenuated by a desired amount, typically between 90 and 100%, in the areas covered by the absorbing layer. The light that passes through some regions of the mask may also be phase shifted by a desired phase angle, typically an integer multiple of 90 degrees. After being collected by the projection optics of the exposure tool, the resulting aerial image pattern is then focused onto the wafers. A light-sensitive material (photoresist or resist) deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well-known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the mask pattern onto the wafer. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture (NA) of the exposure tool times the minimum feature size Wf divided by the wavelength λ, i.e., k1=NA·Wf/λ. There is limited practical flexibility in choosing the exposure wavelength, while the numerical aperture of exposure tools is approaching physical limits. Consequently, the continuous reduction in device feature sizes requires more and more aggressive reduction of the k1 factor in lithographic processes, i.e. imaging at or below the classical resolution limits of an optical imaging system.
New methods to enable low-k1 lithography have used master patterns on the mask that are no longer exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size and placement of pattern features as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns) known as Optical Proximity Correction, or OPC; and the addition of other geometries that are not intended to be replicated on the wafer at all. The sole purpose of these non-printing “assist features,” also known as Sub-Resolution Assisting Features (SRAFs) or scattering bars, is to enhance the printability of the “main features.” The SRAFs are typically small bars (the term “bar” encompasses lines and other geometric shapes) placed close to the main features so that the printability of the main features is more robust against focus and/or dose change. All of these methods are often referred to collectively as Resolution Enhancement Technology (RET). With decreasing k1, the magnitude of proximity effects increases dramatically. In current high-end designs, more and more device layers require RET, and almost every feature edge requires some amount of adjustment to ensure that the printed pattern will reasonably resemble the design intent. The implementation and verification of such extensive RET application is only made possible by detailed full-chip computational lithography process modeling, and the process is generally referred to as model-based RET.
The cost of manufacturing advanced mask sets is steadily increasing. Currently, the cost has already exceeded one million dollars per mask set for an advanced device. In addition, the turn-around time is always a critical concern. As a result, lithography-driven RET design, which assists in reducing both the cost and turn-around time, has become an integral part of semiconductor manufacturing.
As the lithography process entered below the 65 nm node (such as, 28 nm node), leading-edge chip designs have minimum feature sizes smaller than the wavelength of light used in advanced exposure tools. SRAFs become indispensable even if OPC techniques provide good results. Typically, OPC will modify the design layout so that a resist image (RI) contour is close enough to the design target at nominal condition. However, the Process Window (PW) is rather small without any extra features. SRAFs are needed to enhance the printability of the main features across a wider range of defocus and delta dose scenarios in order to maintain adequate process margins in the lithography process.
One method for implementing SRAFs that is widely in use is rule-based SRAF placement using an empirical (manual) rule-generator. In this method, a combination of benchmark test patterns with different SRAF configurations are printed (or simulated) on a wafer. Critical Dimension (CD) is then measured on the wafer, a set of rules for SRAF placement is drawn from the CD comparison, and finally the set of rules is used in SRAF placement for each main feature segment in a design. It should be noted that empirical rule-based SRAF placement requires an efficient mechanism to solve many conflicts between SRAFs derived from different main feature segments.
Another proposed method to generate SRAFs is based on inverse lithography techniques. In this method, the goal is to identify a mask image that minimizes an objective function (also referred to as a “cost function”). The objective function includes the difference between the resulting aerial image and the ideal design target image and also the difference between the aerial image intensity at the design target edge locations and the threshold for contours across wide ranges of defocus and delta dose conditions. To solve this non-linear programming problem, various iterative approaches are used to identify a local minimum solution.
While these methods have demonstrated some successes, their disadvantages have slowed the development cycle and limited their usage. For example, the empirical (manual) rule-generator has the following drawbacks: unable to take into account all possible patterns/spaces/line widths in a limited number of test patterns; high cost and low speed to manufacture the mask, print the wafer, and measure CD; difficulty in measuring the SRAFs' performance across the PW; and difficulty in resolving SRAF conflicts. The inverse lithography based method is also complicated and slow, since it may require quite a few slow iterations to converge. It may also converge to a local optimum, and it is not feasible to use it directly as it generates continuous values for each pixel while only rectangular shaped patterns with mask constraints are manufacturable. In addition, the objective function includes the difference between the whole aerial image and the design target, while in practice, the fidelity of the aerial image contours is of more interest. The focus on pixels deep inside or outside main features may be counterproductive.
Computer models have been created to come up with a faster and efficient SRAF placement algorithm that takes 2D pattern shapes into consideration and optimizes for a desired PW. This technique is called Model-Based Sub-Resolution Assist Feature (MB-SRAF) method. MB-SRAF methods have been exercised as the RET solution for certain applications, such as, for printing trench contacts, vias, and metal layers for 28 nm technology node.
Current MB-SRAF algorithms depend on signal mapping (i.e. measuring signal strength at various locations) to guide SRAF placements. The signal map, known as SRAF Guidance Map (SGM), is derived from variants of image contrast and process focus derivatives. Details of the generation of an SGM can be found in co-pending U.S. patent publication no. 2008/0301620, which is incorporated herein by reference. The current MB-SRAF methods are based on an initial SGM, which may not be optimized for a process window. There is a need for a method that can dynamically optimize the SGM, and can accommodate a large enough process window, while reducing the computational load.